A Novel approach to design secure and reliable SRAM from power analysis attack using power equalizer circuit

被引：0
|
作者：
Sharma, Priyanka [1 ]
Gupta, Aastha [1 ]
Panchal, Ashish [1 ]
Neema, Vaibhav [1 ]
机构：
[1] IET Devi Ahilya Univ, Indore, MP, India
来源：
8TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE, EDTM 2024 | 2024年
关键词：
SRAM; SCA and Power dissipation;
D O I：
10.1109/EDTM58488.2024.10511943
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
Power analysis side channel attacks are very prominent among attackers to extract secret data temporarily stored in SRAM. This paper presents a novel method in which a power equalizer circuit is used in 6T cell to design secure and reliable memory in all three operations. Monte-Carlo simulations of 1000 samples has been performed to obtain data prediction probability which is 0.03%, 1.36% and 1.88% during read, write and hold operations respectively for proposed cell.
引用
收藏
页码：244 / 246
页数：3
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