Impact of Gate Insulator Process on NBTI in FinFETs and Resulting Ring Oscillator Degradation Under Normal and Overclocking Usage Conditions

A device to circuit framework is used to analyse the impact of Replacement Metal Gate (RMG) process optimizations on Negative Bias Temperature Instability (NBTI) in p-FinFETs. Ultra-fast (10 mu s delay) measured threshold voltage shift (Delta V-T) time kinetics is modelled using the BTI Analysis Tool (BAT) framework. Contributions from generated interface (Delta V-IT) and bulk (Delta V-OT) traps and trapping of holes (Delta V-HT) in pre-existing traps are estimated for short time accelerated stress and End-of-life (EOL) at different gate bias (V-G) and temperature (T). Circuit Aging Reliability Analysis Tool (CARAT), a cycle-by-cycle simulation platform that incorporates BAT, is employed to estimate frequency degradation (%Delta f) of Inverter based 21-stage Ring Oscillator (RO) circuits at various fixed bias (V-DD), T, and also for Dynamic Voltage Frequency Scaling (DVFS) conditions. RMG process impact on RO aging is estimated.