Research on heat transfer and flow distribution of parallel-configured microchannel heat sinks for arrayed chip heat dissipation

The heat dissipation ability and compact structure of microchannel flow boiling show great promise for highefficiency heat dissipation in the field of chip cooling. In arrayed chip cooling scenarios, multiple microchannel heat sinks are typically arranged in parallel. Random fluctuations in the heat load of each chip can lead to non-uniform flow distribution and even thermal failure of the chip. However, there are still limited studies on the non-uniform flow distribution in the parallel use of multiple microchannel heat sinks. This study presents an experimental and theoretical study on the boiling heat transfer and flow distribution characteristics of two heat sinks in parallel using HFE-7100. The steady-state test results indicated that the flow distribution characteristics in parallel-configured heat sinks were closely correlated with the flow pattern. In the single-phase region, flow distribution in both heat sinks was primarily influenced by the physical properties of the fluid. The effect of heat flux on non-uniform flow distribution was within 7 %. When one of the heat sinks entered the two-phase region, microchannel resistance characteristics changed significantly, leading to a dramatic increase in non-uniform flow distribution, up to 26.0 %. The critical heat flux (CHF) was triggered prematurely, with a decrease of up to 31.4 %. In dynamic characteristics testing, when both heat sinks were in the two-phase region simultaneously, the increase in heat flux led to greater non-uniformity in the flow distribution of the parallel-configured heat sinks compared to the single-phase region. Furthermore, considering the transition boundary of two-phase flow patterns in microchannels, a prediction model for flow distribution in parallel-configured microchannel heat sinks was proposed, demonstrating good predictive capability. The research provides a reference for the design and optimization of two-phase cooling systems for arrayed chip configurations.