Analysis of power model of multi-core microprocessor architecture

被引：0
|
作者：
Chen Z. [1 ]
Liu C. [2 ]
Hou S. [3 ]
Guo Y. [4 ]
机构：
[1] Institute of Combat Support, Army Academe, Wuxi
[2] College of Computer Science and Electronic Engineering, Hunan University, Changsha
[3] Department of Basic Courses, Information Engineering University, Luoyang
[4] School of Computer, National University of Defense Technology, Changsha
来源：
Zhongnan Daxue Xuebao (Ziran Kexue Ban)/Journal of Central South University (Science and Technology) | 2019年 / 50卷 / 07期
基金：
中国国家自然科学基金;
关键词：
Architecture level; Multi-core processor; Peak power consumption; Process simulator;
D O I：
10.11817/j.issn.1672-7207.2019.07.014
中图分类号：
学科分类号：
摘要：
The FT-SHSim simulation tool platform was used to model the mainstream microprocessor core models SMT and MSS. Using advanced CMOS technology, the simulation experiment of power consumption evaluation at the architecture level obtained the process requirements of different microprocessor structures and the performance and scale required by the same microprocessor structure during different processes. This provided a reference value for process requirements and implementation methods for the early stages of design, improving quality, shortening cycles, and accelerating design convergence. The results show that in the 22 nm process of the minimum line width, the 128-core SMT processor model has a peak power of 116 W and 64-core MSS processor model has a peak power of 161 W. © 2019, Central South University Press. All right reserved.
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页码：1611 / 1618
页数：7
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