Analysis and Hardware Optimization of Lattice Post-Quantum Cryptography Workloads

被引：0
|
作者：
Koteshwara, Sandhya [1 ]
Kumar, Manoj [1 ]
Pattnaik, Pratap [1 ]
机构：
[1] IBM TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA
来源：
PROCEEDINGS OF THE 9TH INTERNATIONAL WORKSHOP ON HARDWARE AND ARCHITECTURAL SUPPORT FOR SECURITY AND PRIVACY, HASP 2020 | 2020年
关键词：
Post Quantum Cryptography; lattice-based cryptography; Learning With Errors; PQC; LWE;
D O I：
10.1145/3458903.3458905
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The mathematical constructs, nature of computations and challenges in optimizing lattice post-quantum cryptographic algorithms on modern many-core processors are discussed in this paper. Identification of time-consuming functions and subsequent hardware optimization using vector units and hardware accelerators of one of the candidates, CRYSTALS-Kyber, leads to performance improvement of around 52% for its SHA3 variant and 83% for its AES variant. Detailed Cycles-per-Instruction (CPI) stack breakdown before and after optimization indicates a CPI of around 0.5 and dominance of load/store operations in these workloads.
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页数：9
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