Design and implementation of an efficient CNN accelerator for low-cost FPGAs

被引：7

作者：

Xu Y. ^{[1
]}

Wang S. ^{[1
]}

Li N. ^{[1
]}

Xiao H. ^{[1
]}

机构：

[1] School of Microelectronics, Hefei University of Technology, Hefei

来源：

IEICE Electronics Express | 2022年 / 19卷 / 19期

基金：

中国国家自然科学基金;

关键词：

convolutional neural network; FPGA; hardware accelerator;

D O I：

10.1587/elex.19.20220370

中图分类号：

学科分类号：

摘要：

This paper proposes a computation-array-centered dataflow, which adjusts the convolution with different kernel sizes to a unified computing manner and reduces the dimension of computation array from 2D to 1D, so as to maximize the utilization of the computation elements offered by the accelerator. Furthermore, a single unit multiple data (SUMD) strategy is proposed to effectively alleviate the mismatch between the quantized data and the hardware resources with fixed bit width on FPGA. As a case study, an 8-bit MobileNetV2 model has been implemented on the low-cost ZYNQ XC7Z020 FPGA, whose FPS/DSP and GOPS/DSP achieve upto 0.55 and 0.35 respectively. © 2022 The Institute of Electronics.

引用

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