On Minimizing Charge Injection Error Using Multi-Dummy Switches With Enhanced Linearity

The paper proposes an ameliorated methodology to minimize the effect of charge injection over a wide input common -mode range. Instead of a conventional single dummy switch compensation [1], the multi -dummy switches are proposed and employed to eradicate the injected charge on to the sampling capacitor. A detailed methodology is presented to compensate the charge injection in a MOS switch. The closed -form equations are derived mathematically to substantiate the proposed technique. For the proof -of -concept, a track -andhold (T/H) stage has been simulated in 0.18 mu m CMOS technology with the proposed technique for a 10 -bit resolution. The proposed technique based T/H stage exhibits the spurious free dynamic range (SFDR) of 62.6 dB, effective number of bits (ENOB) of 9.36, peak input -referred third -order intercept point (IIP3) of 13.02 dBm and an input -referred 1 dB compression point (P1dB) of 3.8 dBm at 1.074 MHz input frequency, sampled at 100 MSa/s. The performance of the proposed method is compared with the existing single dummy switch compensation method where our technique shows 88.8% compensation in minimizing the charge injection error and 272% improvement in dynamic linearity. Moreover, the presented technique quantifies 9x improvement in mean percentage error (MPE) when simulated across the various process corners and rail -to -rail input common -mode voltage.