Asynchronous Architecture of Stochastic Computing Spiking Neuron Network

被引：0
|
作者：
Gao Y. [1 ]
Chen Y. [1 ]
Zhu Y. [1 ]
Xue X. [1 ]
Li H. [1 ]
机构：
[1] College of Electrical and Information Engineering, Beihang University, Beijing
来源：
Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics | 2022年 / 34卷 / 04期
关键词：
Asynchronous circuit; Spiking neural network; Stochastic computing;
D O I：
10.3724/SP.J.1089.2022.19440
中图分类号：
学科分类号：
摘要：
Stochastic computing encodes binary numbers into stochastic pulse sequences in operating, which takes advantages of low power consumption and low resource usage. The application of stochastic computing in the design of spiking neural network (SNN) accelerator is beneficial to realize brain-like operation. In order to realize the low-power edge calculation of neural network, an asynchronous architecture using stochastic computing is designed, which can be used to realize the operation of full connected SNN. Cross array controlled by asynchronous micro-pipeline is implemented to achieve the leaky integrate and fire (LIF) neuron model. In the input layer of SNN, input values are encoded into stochastic pulses, and the synaptic weights and input pulses are calculated through accumulation, and the attenuation of neuron membrane potential value is realized based on logic calculation. The event-driven coding and the transmission of stochastic pulse are controlled by the asynchronous architecture, which can reduce the power consumption of SNN operation; The proposed architecture achieves an operation of SNN with 784 input and 10 output, which is verified on Xilinx KCU116 platform and achieves a peak throughput of 78.4 GSOPS and an energy efficiency of 137.47 GSOPS/W. © 2022, Beijing China Science Journal Publishing Co. Ltd. All right reserved.
引用
收藏
页码：522 / 526
页数：4
相关论文
共 8 条
  • [1] Akopyan F, Sawada J, Cassidy A, Et al., TrueNorth: design and tool flow of a 65 mW 1 million neuron programmable neurosynaptic chip, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34, 10, pp. 1537-1557, (2015)
  • [2] Cheung K, Schultz S R, Luk W., NeuroFlow: a general purpose spiking neural network simulation platform using customizable processors, Frontiers in Neuroscience, 9, (2015)
  • [3] Pani D, Meloni P, Tuveri G, Et al., An FPGA platform for real-time simulation of spiking neuronal networks, Frontiers in Neuroscience, 11, (2017)
  • [4] Diehl P U, Zarrella G, Cassidy A, Et al., Conversion of artificial recurrent neural networks to spiking neural networks for low-power neuromorphic hardware, Proceedings of the IEEE International Conference on Rebooting Computing, pp. 1-8, (2016)
  • [5] Kondo Y, Sawada Y., Functional abilities of a stochastic logic neural network, IEEE Transactions on Neural Networks, 3, 3, pp. 434-443, (1992)
  • [6] Kohler E, Morris R, Chen B J, Et al., The Click modular router, ACM Transactions on Computer Systems, 18, 3, pp. 263-297, (2000)
  • [7] Cho S G, Beigne E, Zhang Z., A 2048-neuron spiking neural network accelerator with neuro-inspired pruning and asynchronous network on chip in 40nm CMOS, Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 1-4, (2019)
  • [8] Zhang J L, Wu H, Wei J S, Et al., An asynchronous reconfigurable SNN accelerator with event-driven time step update, Proceedings of the IEEE Asian Solid-State Circuits Conference, pp. 213-216, (2019)
1