LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA

被引：0

作者：

Xie T. ^{[1
,2
]}

Li B. ^{[1
]}

Yang M. ^{[1
]}

Yan Z. ^{[1
]}

机构：

[1] School of Electronics and Information, Northwestern Polytechnical University, Xi'an

[2] China Academy of Space Technology(Xi'an), Xi'an

来源：

Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University | 2019年 / 37卷 / 02期

关键词：

DVB-S2; standard; FPGA; High speed LDPC decoder; Rate-compatible;

D O I：

10.1051/jnwpu/20193720299

中图分类号：

学科分类号：

摘要：

A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase lower triangular (TST) sub-matrix is obtained. The QC and TST are designed separately, therefore the successful experience of the most popular Quasi-Cyclic (QC) LDPC decoder architecture can be drawn on. While for TST sub-matrix, the variable nodes updating only need to be considered and the check nodes updating is realized compatibility with QC sub-matrix. Based on the proposed architectures, a multi-rate LDPC decoder implemented on Xilinx XC7VX485T FPGA can achieve the maximum decoding throughput of 2.5 Gbit/s at the 20 iterations when the operating frequency is 250 MHz, which demonstrates the highest throughput compared with the state-of-the-art works. © 2019 Journal of Northwestern Polytechnical University.

引用

页码：299 / 307

页数：8

共 13 条

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