FSS: algorithm and neural network accelerator for style transfer

被引:0
|
作者
Yi LING [1 ]
Yujie HUANG [1 ,2 ]
Yujie CAI [1 ,2 ]
Zhaojie LI [1 ,2 ]
Mingyu WANG [1 ]
Wenhong LI [1 ]
Xiaoyang ZENG [1 ]
机构
[1] State Key Laboratory of ASIC & System,Fudan University
[2] Shanghai Explore X Technology Co.,Ltd.
基金
中国国家自然科学基金;
关键词
D O I
暂无
中图分类号
TP183 [人工神经网络与计算]; TP391.41 [];
学科分类号
080203 ;
摘要
Neural networks(NNs), owing to their impressive performance, have gradually begun to dominate multimedia processing. For resource-constrained and energy-sensitive mobile devices, an efficient NN accelerator is necessary. Style transfer is an important multimedia application. However, existing arbitrary style transfer networks are complex and not well supported by current NN accelerators, limiting their application on mobile devices. Moreover, the quality of style transfer needs improvement. Thus, we design the Fast Style system(FSS), where a novel algorithm and an NN accelerator are proposed for style transfer. In FSS, we first propose a novel arbitrary style transfer algorithm, Fast Style. We propose a light network that contributes to high quality and low computational complexity and a prior mechanism to avoid retraining when the style changes. Then, we redesign an NN accelerator for Fast Style by applying two improvements to the basic NVIDIA deep learning accelerator(NVDLA) architecture. First, a flexible dat FSM and wt FSM are redesigned to enable the original data path to perform other operations(including the GRAM operation)by software programming. Moreover, statistics and judgment logic are designed to utilize the continuity of a video stream and remove the data dependency in the instance normalization, which improves the accelerator performance by 18.6%. The experimental results demonstrate that the proposed Fast Style can achieve higher quality with a lower computational cost, making it more suitable for mobile devices. The proposed NN accelerator is implemented on the Xilinx VCU118 FPGA under a 180-MHz clock. Experimental results show that the accelerator can stylize 512×512-pixel video with 20 FPS, and the measured performance reaches up to 306.07 GOPS. The ASIC implementation in TSMC 28 nm achieves about 22 FPS in the case of a 720-p video.
引用
收藏
页码:253 / 266
页数:14
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