DESIGN OF CMOS CIRCUITS FOR STUCK-OPEN FAULT TESTABILITY

CMOS circuits present severe problems in the detection of transistor stuck-open faults. In CMOS circuits, the transistor stuck-open (s-open) faults cause sequential behavior, and hence two- or multipattern sequences are used to detect s-open faults. Furthermore, two- or multipattern sequences may fail to detect a fault in several situations. The available methods for augmenting CMOS gates require a large amount of extra hardware and still are not able to detect a fault deterministically. A new design is presented which requires a single transistor to improve the circuit testability. The proposed design is highly testable and ensures the detection of s-open faults while a single test vector is used during testing. These tests are not invalidated due to the timing skews, glitches, or charge redistribution among the internal nodes.