AREA-EFFICIENT DIMINISHED-1 MULTIPLIER FOR FERMAT NUMBER-THEORETIC TRANSFORM

A novel VLSI implementation of diminished-1 multipliers is proposed. The new implementation obviates the need for code translation from diminished-1 into regular binary representation and, consequently, a reduction in the required chip area is achieved. For a multiplier where the modulus involved is F4, the fifth Fermat number, a reduction of about 16% in the chip area, is achieved relative to that required by the conventional diminished-1 multiplier. Diminished-1 multipliers are indispensable for the implementation of Fermat number transforms.