A 3-LEVEL ASYNCHRONOUS PROTOCOL FOR A DIFFERENTIAL 2-WIRE COMMUNICATION LINK

被引：7
|
作者：
SVENSSON, C
YUAN, JR
机构：
[1] LSI Design Center, IFM, Linkoping University
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1994年 / 29卷 / 09期
关键词：
D O I：
10.1109/4.309909
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A differential two-wire communication link with a 3-level asynchronous protocol is introduced. The proposed 3-level code contains information of both data and clock. Since only one edge is needed for each bit, the bandwidth of a link is efficiently utilized. The power consumption is reduced by the low-swing differential two-wire link and is further reduced by a 3-level code. The speed of the protocol is expected to reach 1 Gb/s in a 1.2-mum CMOS process.
引用
收藏
页码：1129 / 1132
页数：4
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