AN ATM SWITCH ARCHITECTURE FOR PROVISION OF INTEGRATED BROAD-BAND SERVICES

In this paper, we try to envision some qualitative performance targets to be fulfilled for the service classes proposed by CCITT for the future B-ISDN and propose a nonblocking self-routing ATM switching architecture that is able to fulfill the different performance figures of each class. In order to exploit the service integration accomplished by ATM switches, the switching bandwidth is allocated at two different levels; that is, at call level and cell level. This allocation gives the flexibility of letting lower priority services use the reserved bandwidth left temporarily unused by higher priority services. The proposed architecture adopts mixed input-output queueing. Input queueing is particularly suited to the definition of "internal frame structures," that allows us to guarantee for specific services (such as circuit emulation) absence of cell loss due to congestion. Output queueing makes it possible to implement in hardware a switching speedup that practically removes the performance degradation due to the well-known head-of-line blocking phenomenon typical of input queueing.