A verified information-flow architecture

被引:9
|
作者
de Amorim, Arthur Azevedo [1 ]
Collins, Nathan [7 ]
DeHon, Andre [1 ]
Demange, Delphine [5 ]
Hritcu, Catalin [3 ]
Pichardie, David [6 ]
Pierce, Benjamin C. [1 ]
Pollack, Randy [4 ]
Tolmach, Andrew [2 ]
机构
[1] Univ Penn, Philadelphia, PA 19104 USA
[2] Portland State Univ, Portland, OR 97207 USA
[3] INRIA, Paris, France
[4] Harvard Univ, Boston, MA 02115 USA
[5] Univ Rennes 1, IRISA, Rennes, France
[6] ENS Rennes, IRISA, Rennes, France
[7] Galois Inc, Portland, OR USA
关键词
Security; clean-slate design; tagged architecture; information-flow control; formal verification; refinement;
D O I
10.3233/JCS-15784
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
SAFE is a clean-slate design for a highly secure computer system, with pervasive mechanisms for tracking and limiting information flows. At the lowest level, the SAFE hardware supports fine-grained programmable tags, with efficient and flexible propagation and combination of tags as instructions are executed. The operating system virtualizes these generic facilities to present an information-flow abstract machine that allows user programs to label sensitive data with rich confidentiality policies. We present a formal, machine-checked model of the key hardware and software mechanisms used to dynamically control information flow in SAFE and an end-to-end proof of noninterference for this model. We use a refinement proof methodology to propagate the noninterference property of the abstract machine down to the concrete machine level. We use an intermediate layer in the refinement chain that factors out the details of the information-flow control policy and devise a code generator for compiling such information-flow policies into low-level monitor code. Finally, we verify the correctness of this generator using a dedicated Hoare logic that abstracts from low-level machine instructions into a reusable set of verified structured code generators.
引用
收藏
页码:689 / 734
页数:46
相关论文
共 50 条
  • [1] A Verified Information-Flow Architecture
    de Amorim, Arthur Azevedo
    Collins, Nathan
    DeHon, Andre
    Demange, Delphine
    Hritcu, Catalin
    Pichardie, David
    Pierce, Benjamin C.
    Pollack, Randy
    Tolmach, Andrew
    [J]. ACM SIGPLAN NOTICES, 2014, 49 (01) : 165 - 178
  • [2] A verified static information-flow control library
    Vassena, Marco
    Russo, Alejandro
    Buiras, Pablo
    Waye, Lucas
    [J]. JOURNAL OF LOGICAL AND ALGEBRAIC METHODS IN PROGRAMMING, 2018, 95 : 148 - 180
  • [3] INFORMATION-FLOW
    不详
    [J]. NATION, 1981, 233 (04) : 101 - 102
  • [4] Information-flow models for shared memory with an application to the PowerPC architecture
    Adir, A
    Attiya, H
    Shurek, G
    [J]. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2003, 14 (05) : 502 - 515
  • [5] IMPROVING THE INFORMATION-FLOW
    HAKE, DL
    [J]. BULLETIN OF THE ATOMIC SCIENTISTS, 1962, 18 (09) : 21 - 22
  • [6] MAKING INFORMATION-FLOW
    MARTIN, JM
    [J]. MANUFACTURING ENGINEERING, 1989, 102 (05): : 75 - 78
  • [7] Information-flow Interfaces
    Bartocci, Ezio
    Ferrere, Thomas
    Henzinger, Thomas A.
    Nickovic, Dejan
    da Costa, Ana Oliveira
    [J]. FUNDAMENTAL APPROACHES TO SOFTWARE ENGINEERING, FASE 2022, 2022, 13241 : 3 - 22
  • [8] Information-flow interfaces
    Bartocci, Ezio
    Ferrere, Thomas
    Henzinger, Thomas A.
    Nickovic, Dejan
    Oliveira da Costa, Ana
    [J]. FORMAL METHODS IN SYSTEM DESIGN, 2024,
  • [9] PATIENT INFORMATION-FLOW
    BLEKELI, RD
    [J]. INFORMATION PRIVACY, 1980, 2 (01): : 37 - 41
  • [10] INFORMATION-FLOW IN VLSI DESIGN
    RATHMELL, JG
    [J]. INTEGRATION-THE VLSI JOURNAL, 1986, 4 (02) : 185 - 191