A BIPOLAR POPULATION COUNTER USING WAVE PIPELINING TO ACHIEVE 2.5 X NORMAL CLOCK FREQUENCY

被引:16
|
作者
WONG, DC
DEMICHELI, G
FLYNN, MJ
HUSTON, RE
机构
[1] STANFORD UNIV,DEPT COMP SCI,STANFORD,CA 94305
[2] LTX CORP,DIV TRILLIUM,SAN JOSE,CA 95134
基金
美国国家科学基金会; 美国国家航空航天局;
关键词
computer design; computer-aided design; digital circuits; fine tuning; hardware; maximal-rate pipelining; power optimization; rough tuning; Wave pipelining;
D O I
10.1109/4.133161
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Wave pipelining is a technique for pipelining digital systems that can increase clock frequency in practical circuits without increasing the number of storage elements. In wave pipelining, multiple coherent waves of data are sent through a block of combinational logic by applying new inputs faster than the delay through the logic. The throughput of a 63-b CML population counter was increased from 97 to 250 MHz using wave pipelining. The internal circuit is flowthrough combinational logic. Novel CAD methods have balanced all in-put-to-output paths to about the same delay. This allows multiple data waves to propagate in sequence when the circuit is clocked faster than its propagation delay.
引用
收藏
页码:745 / 753
页数:9
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