RISC PROCESSORS IN A MASSIVELY PARALLEL DATABASE MACHINE

被引：0
|
作者：
LI, QA
RISHE, N
TAL, D
机构：
[1] School of Computer Science, Florida International University, Miami
来源：
MICROPROCESSORS AND MICROSYSTEMS | 1990年 / 14卷 / 06期
关键词：
database machines; interprocessor communication; microsystems; transputers;
D O I：
10.1016/0141-9331(90)90107-7
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The paper presents an application of RISC processors in a massively parallel database machine (LSDM). Depending on the configuration, the database machine can contain a few thousand processors, each of which is equipped with a disc drive. The database model used is the semantic binary model. The combination of the database model and the architecture of LSDM provides an environment where both massively parallel computation and massively parallel I/O are possible. This paper analyses the characteristics of LSDM and argues that RISC processors are the best choice for the database machine. This machine is presented as further evidence of the potential of RISC architecture. Performance evaluation and simulation results based on the characteristics of Inmos transputers are also presented. © 1990.
引用
收藏
页码：351 / 356
页数：6
相关论文
共 50 条
  • [1] ARCHITECTURE FOR A MASSIVELY PARALLEL DATABASE MACHINE
    RISHE, N
    TAL, D
    LI, Q
    [J]. MICROPROCESSING AND MICROPROGRAMMING, 1989, 25 (1-5): : 33 - 38
  • [2] ADVANTAGES OF MASSIVELY PARALLEL PROCESSORS
    ISHII, M
    [J]. FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 1993, 29 (01): : 3 - 5
  • [3] Massively Parallel Server Processors
    Agrawal, Varun
    Dinani, Mina Abbasi
    Shui, Yuxuan
    Ferdman, Michael
    Honarmand, Nima
    [J]. IEEE COMPUTER ARCHITECTURE LETTERS, 2019, 18 (01) : 75 - 78
  • [4] IBM IS JUMPING INTO MASSIVELY PARALLEL PROCESSORS
    MCLEOD, J
    [J]. ELECTRONICS-US, 1992, 65 (11): : 9 - 9
  • [5] Lanczos algorithms for massively parallel processors
    Szularz, M
    Clint, M
    Weston, JS
    [J]. PARALLEL COMPUTING: FUNDAMENTALS, APPLICATIONS AND NEW DIRECTIONS, 1998, 12 : 619 - 622
  • [6] VLSI DESIGN FOR MASSIVELY PARALLEL SIGNAL PROCESSORS
    KUNG, SY
    ANNEVELINK, J
    [J]. MICROPROCESSORS AND MICROSYSTEMS, 1983, 7 (10) : 461 - 468
  • [7] Broadband monitoring simulation with massively parallel processors
    Trubetskov, Michael
    Amotchkina, Tatiana
    Tikhonravov, Alexander
    [J]. ADVANCES IN OPTICAL THIN FILMS IV, 2011, 8168
  • [8] Massively parallel processors generator for reconfigurable system
    Hamada, T
    Nakasato, N
    [J]. FCCM 2005: 13TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS, 2005, : 329 - 330
  • [9] PIO: Parallel I/O system for massively parallel processors
    Boku, T
    Matsubara, M
    Itakura, K
    [J]. HIGH-PERFORMANCE COMPUTING AND NETWORKING, 2001, 2110 : 383 - 392
  • [10] A RISC CENTRAL PROCESSING UNIT FOR A MASSIVELY PARALLEL ARCHITECTURE
    CAPPELLO, F
    BECHENNEC, JL
    ETIEMBLE, D
    [J]. MICROPROCESSING AND MICROPROGRAMMING, 1990, 30 (1-5): : 33 - 39
12345