A 5-NS 32-K X8/X9 BI-CMOS TTL SRAM WITH ALTERNATED BIT-LINE LOAD ARCHITECTURE

被引：0

作者：

OHBAYASHI, S ^{[1
]}

SHIOMI, T ^{[1
]}

MATSUO, R ^{[1
]}

SUMI, T ^{[1
]}

HONDA, H ^{[1
]}

ISHIGAKI, Y ^{[1
]}

UGA, K ^{[1
]}

ISHIDA, M ^{[1
]}

KOHNO, Y ^{[1
]}

机构：

[1] MITSUBISHI ELECTR CORP,LSI LAB,ITAMI,HYOGO 664,JAPAN

来源：

ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS | 1994年 / 77卷 / 02期

关键词：

BI-CMOS; SRAM; TTL; CMOS; BIPOLAR; BIT-WIDE;

D O I：

10.1002/ecjb.4420770208

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An ultrahigh-speed 32 K x8/x9 TTL bi-CMOS SRAM with a 5-ns standard access time was developed using a five-layer polysilicon/two-layer aluminum 0.6-mu m bi-CMOS process with 4.2 x 5.6-mu m(2) 4-M SRAM-class small-size memory cells, ultrahigh capacity, self-aligned bipolar electrodes with 18.5-GHz cutoff frequency and 0.6-mu m/0.7-mu m (nMOS/pMOS) gate-length MOS transistors. This fast access time was achieved by using center power pin-out to reduce output noise, a major problem in the TTL SRAM, together with alternated bit line load architecture, a memory array architecture well suited to center power pin-out. Also used were a bit-line load circuit for rapid precharging of the bit line and a high-speed wired-OR column-sensing circuit.

引用

页码：65 / 76

页数：12