LAYOUT-DEPENDENT FAULT ANALYSIS AND TEST SYNTHESIS FOR CMOS CIRCUITS

An arithmetic approach to extract the potential physical defects from the specific circuit layout of an integrated circuit is proposed. The defects subsequently are transformed into circuit faults and weighted according to their likelihood of occurrence. Based on these open and short faults extracted from CMOS layouts, an automatic test pattern generator is implemented. The test synthesis of some combinational CMOS benchmark circuits illustrates the superiority of our new CMOS fault models and their application to test pattern generation as compared with the classical stuck-at fault models.