共 50 条
- [1] High-Level Radio Protocol Specifications to Efficient Low-Level Implementations via Partial Evaluation [J]. PROCEEDINGS OF THE 6TH ACM SIGPLAN INTERNATIONAL WORKSHOP ON FUNCTIONAL HIGH-PERFORMANCE COMPUTING (FHPC '17), 2017, : 1 - 11
- [2] Verifying Low-Level Implementations of High-Level Datatypes [J]. COMPUTER AIDED VERIFICATION, PROCEEDINGS, 2010, 6174 : 306 - 320
- [3] Verification of scheduling in high-level synthesis [J]. IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2006, : 141 - +
- [4] Formal Verification of High-Level Synthesis [J]. PROCEEDINGS OF THE ACM ON PROGRAMMING LANGUAGES-PACMPL, 2021, 5 (OOPSLA):
- [5] A Survey of Verification for High-level Synthesis [J]. Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics, 2021, 33 (02): : 287 - 297
- [7] H-DBUG: A high-level debugging framework for protocol verification using assertions [J]. INDICON 2005 Proceedings, 2005, : 115 - 118
- [8] High-level design of a pull protocol [J]. PROCEEDINGS OF THE ISCA 20TH INTERNATIONAL CONFERENCE ON COMPUTERS AND THEIR APPLICATIONS, 2005, : 66 - 73
- [9] Mutation-based validation of high-level microprocessor implementations [J]. NINTH IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS, 2004, : 81 - 86
- [10] High-level modeling and verification of cellular signaling [J]. 2016 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP (HLDVT), 2016, : 162 - 169