RECONFIGURATION STRATEGIES FOR VLSI PROCESSOR ARRAYS AND TREES USING A MODIFIED DIOGENES APPROACH

Reconfiguration strategies in VLSI processor arrays have been advocated in the recent literature as a means of achieving higher production yield and higher reliability. In this paper, we present new reconfiguration techniques for rectangular arrays and trees that are modifications of the Diogenes approach proposed earlier by Rosenberg et al. These techniques reduce the overheads incurred in the earlier Diogenes schemes. We present two schemes for reconfiguring rectangular arrays and a scheme for reconfiguring trees. For the analysis of the different schemes presented in this paper, we assume that a processor has a square layout. The first scheme for reconfiguring an N x N rectangular array uses tau additional rows and c additional columns. It takes O(tau(N + tau)(N + c) square-root A + (N + tau)(N + c)A) area, where A is the area of a single processor. The scheme guarantees reconfiguration as long there are at most c columns that have more than tau-faulty processors. The second scheme uses S spare processors and O((N2 + S)kappa-square-root A + (N2 + S)A) area. Here kappa is a parameter of the design. It guarantees reconfiguration as long as there are enough spare processors, and in any window of N processors in a particular linearization there are at most kappa-faulty processors. The scheme for reconfiguring a tree can tolerate as many faults as the number of spare processors S. The design uses O((N + S)log(N) square-root A + (N + S)A) area. The link length, even in the case of faults, is O(square-root N(log N + square-root A)).