A FLOATING-POINT CELL LIBRARY AND A 100-MFLOPS IMAGE SIGNAL PROCESSOR

A new floating-point cell library for image signal processors has been developed [1]. The library includes a floating-point arithmetic logic unit (ALU), a floating-point multiplier (MPY), an instruction RAM, and a data register file. It has been designed for high-speed operation, which allows the development of a high-performance image signal processor easily. A new adder-subtracter and a new bit alignment circuit have been developed for the ALU. As an application of the library, a new type of vector processor, which includes two ALU's, an MPY, an instruction RAM, and a register file, has been developed. It has a peak performance of 100 MFLOPS at 33 MHz. It is suitable for large-scale image processing, such as FFT, DCT, VQ, and so on. A 1.2-mu-m CMOS fabrication technology with a 1.0-mu-m gate length was used. Other circuits except the floating-point library cells were synthesized by a logic synthesizer. To achieve high-speed operation of the synthesized circuits, a new logic synthesis and optimization technique based on implicit don't-care information in register-transfer-level hardware descriptions has been developed. The high-performance image signal processor has been successfully developed by using the new floating-point cell library and the new logic synthesis and optimization technique.