When designing digital hardware for a given signal processing algorithm, one must ensure that signals arrive at the appropriate points of the implementation at the right times, so that they are operated upon as specified in the algorithm. It is easy to err even for systems of moderate size and complexity, and a single error could cause complete garbage to be output. This problem is particularly severe for bit-serial designs. Also, having obtained a correct implementation, it is not always easy to see how to improve it. In this paper a systematic technique is presented to derive correct schedules for a synchronous digital system, given a signal flow graph for an algorithm. It is also shown how to use this technique to derive designs that are optimal in having the lowest latency, the highest throughput, or the smallest number of registers. The same technique can also be used to verify digital systems that have already been designed.
