PARALLEL PROCESSING ARCHITECTURE FOR THE EFFICIENT USE OF MEMORY IN IMAGE-PROCESSING APPLICATIONS

A parallel processor architecture for image processing applications is presented. The main idea behind this architecture is to carry out image processing computations in a highly parallel manner by dividing the executable instructions and the memory operations such that they may be executed concurrently. As a result, the proposed architecture keeps both the processor and the memory system as busy as possible, thereby obtaining faster response time than for conventional parallel architectures. The proposed architecture consists of an array of processing elements, a system control unit, an interconnection network and memory modules. Each processing element contains two central processing units: One is responsible for the execution of all nonmemory operations, the other is responsible for all memory operations. We develop an analytical method to evaluate the overall performance of the proposed architecture. Also presented are some algorithms suitable for the proposed architecture and an analysis of their performance compared to a conventional system.