CMOS pixel development for the ATLAS experiment at the High Luminosity LHC

To cope with the rate and radiation environment expected at the HL-LIIC, new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: high-voltage enabling technologies that allow to use high depletion voltages, high-resistivity wafers for large depletion depths; radiation-hard processes that allow for CMOS electronics embedded into the sensor substrate. Since 2014, several groups in the ATLAS experiment are actively pursuing CMOS pixell-tkD within an ATLAS Demonstrator program for sensor design and characterisations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high-rate, fast timing and high-radiation operation at LHC. For this, a number of technologies have been explored and characterised.