MODELING OF PARASITIC INTERCONNECTION INDUCTANCES ON THE GAAS-BASED VLSICS

Parasitic inductances associated with the interconnections in high density environments have become one of the primary factors in the evolution of the high speed VLSI technology. We have carried out a computer-efficient simulation and developed the related computer software to determine the parasitic inductances associated with the single-, bi-and tri-level high density interconnections on the GaAs-based VLSIC's. The self and coupling interconnection inductances have been determined by a network analogue method developed for the finite-length interconnections, open substrates and finite dimensions of the bottom ground plane. Related computer software modules have been developed and run successfully on the mainframe computers. For a given set of the interconnection dimensions and other parameters, the algorithm takes less than 1 minute of the computer processing time on a mainframe computer. The modules have been used to study the dependences of the parasitic inductances on the interconnection parameters such as their length, width, separation, interlevel distance and the substrate thickness.