Static Power Analysis and Estimation in Ternary Content Addressable Memory Cells

Ternary CAM (Content Addressable Memory) circuits are predominantly used in current generation network routers and switches. Fast IP (Internet Protocol) data transfer requirements have lead to the increase in usage of TCAM cells for bit-searches. To improve the speed of the CMOS circuits, transistors are being scaled down to nanoscale regime. At such small geometries transistors dissipate significant leakage power in static mode. Consequentially the leakage power consumed by these circuits is an emerging design constraint. In this paper, we analyze the static leakage power components in a TCAM cell and explore four different implementations of the TCAM cell to identify the best model. Each of the TCAM cell designs was prototyped in MAGIC and the parasitics were extracted to perform the SPICE simulations (for 65 nm and 45 nm). We analyze the different components that are contributors to the leakage current in a TCAM cell and propose an ad-hoc approach to estimate the overall leakage current in the TCAM. The results using the ad-hoc approach are within a variance of 3.2%-7.3% of the expected norm. The TCAM cells using NOR compare circuitry proved to consume less static leakage current than the NAND based circuits. The Hybrid NAND-NOR match line (ML) TCAM proved the most leakage efficient of the four cells. We also implemented a combination of high and low threshold voltage devices in each of the TCAM models. Using high threshold voltage devices as access transistors and low threshold voltage devices as drive transistors curbed the leakage current.