A heterogeneous computer vision architecture: Implementation issues

The prototype of a heterogeneous architecture is currently being built. The architecture is aimed at video-rate computing and is based on a message passing MIMD topology at the top level-transputer based-and on VLSI associative processor arrays (APA, SIMD structure) for low level image processing tasks. The APA structure is implemented through a set of 4 VLSI chips (GLiTCH) containing 64 1-bit processing elements each. This communication addresses some issues concerning the implementation of the first prototype, namely those related to: the design and integration of the APA controller unit, which provides the required interface between the APA, the MIMD topology and the video image interface; the evaluation of the GLiTCH chip through an emulator based on transputers and fast programmable devices; the emulator was designed to be flexible enough to evaluate later modifications to the GLiTCH design; the design of an integrated set of software development tools containing a structured editor-syntax oriented, with a visual interface/programmin, interface-and a cross compiler and debugger.