VHDL/S - INTEGRATING STATECHARTS, TIMING DIAGRAMS, AND VHDL

VHDL/S, the language being developed and employed in the FORMAT project, integrates VHDL, temporal logic, and, as graphical formalisms, timing diagrams and state based specifications into a single framework for specification and verification of reactive behaviour, in particular on the system level. Timing diagrams, like the temporal logic they are based upon, are declarative in nature and comply to a compositional proof methodology that employs automated verification techniques. State based specifications, as an operational language, complement VHDL, with which they share syntactical elements and the fundamental notion of time.