SYSTEM-LEVEL SPECIFICATION AND DESIGN USING VHDL A CASE-STUDY

This paper examines a sample top-down design of a simple CPU starting with a system-level specification in VHDL and ending with an RT-level VHDL description that suits a commercial synthesis tool. Based on the requirement specification captured in a natural language, the design process starts with the creation of a system-level VHDL model, continues with several partitioning steps on system level and the transformation step from system down to RT level, and proceeds over several RT-level optimizations to the final VHDL description. Some of the RT-level optimizations are new in this context. The case study demonstrates the advantages of using VHDL for system-level specification and design and describes a design path comprising both manual interaction and state-of-the-art EDA tools.