BIT CONVEYORS ON VLSI FOR DIGITAL SIGNAL-PROCESSING

被引：0

作者：

BAJKOV, VD

BULGAKOVA, SD

机构：

来源：

AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA | 1990年 / 06期

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

引用

页码：48 / 52

页数：5

共 50 条

[1] ADVANCED VLSI IN DIGITAL SIGNAL-PROCESSING
ROHR, P
[J]. ABSTRACTS OF PAPERS OF THE AMERICAN CHEMICAL SOCIETY, 1980, 180 (AUG): : 2 - COMP
[2] ARCHITECTURES FOR VLSI CIRCUITS IN DIGITAL SIGNAL-PROCESSING
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[J]. COMPUTER NETWORKS AND ISDN SYSTEMS, 1982, 6 (03): : 225 - 227
[3] VLSI DESIGN METHODOLOGIES FOR DIGITAL SIGNAL-PROCESSING
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[J]. EIGHTH BIENNIAL UNIVERSITY/GOVERNMENT/INDUSTRY MICROELECTRONICS SYMPOSIUM, 1989, : 246 - 251
[4] A BIT-SERIAL VLSI ARCHITECTURAL METHODOLOGY FOR SIGNAL-PROCESSING
LYON, RF
[J]. COMPUTER NETWORKS AND ISDN SYSTEMS, 1982, 6 (03): : 228 - 228
[5] VLSI SYSTOLIC MULTIPLIER AND ADDER FOR DIGITAL SIGNAL-PROCESSING
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[J]. SIGNAL PROCESSING, 1991, 23 (02) : 205 - 213
[6] APPLYING DIGITAL VLSI TECHNOLOGY TO RADAR SIGNAL-PROCESSING
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[J]. MICROWAVE JOURNAL, 1986, 29 (01) : 129 - &
[7] A BIT-SERIAL ARCHITECTURE FOR DIGITAL SIGNAL-PROCESSING
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[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1985, 32 (03): : 289 - 291
[8] VLSI SYSTOLIC ARRAY FOR SRIF DIGITAL SIGNAL-PROCESSING ALGORITHM
IWAMI, K
TANAKA, K
[J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1994, E77A (09) : 1475 - 1483
[9] DUAL SYSTOLIC ARCHITECTURES FOR VLSI DIGITAL SIGNAL-PROCESSING SYSTEMS
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[J]. IEEE TRANSACTIONS ON COMPUTERS, 1986, 35 (10) : 916 - 923
[10] VLSI PROGRAMMABLE DIGITAL-FILTER FOR VIDEO SIGNAL-PROCESSING
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GOLLA, C
MICELI, S
[J]. JOURNAL OF VLSI SIGNAL PROCESSING, 1993, 6 (03): : 219 - 231

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