共 50 条
- [1] CONVERGENT LAYOUT OPTIMIZATION FOR DEEP-SUBMICRON DESIGNS ELECTRONIC ENGINEERING, 1995, 67 (821): : S41 - &
- [2] Characterizing substrate coupling in deep-submicron designs IEEE DESIGN & TEST OF COMPUTERS, 2002, 19 (02): : 4 - 15
- [5] Revolutionizing manufacturing processes in very deep-submicron designs IEEE DESIGN & TEST OF COMPUTERS, 2004, 21 (03): : 181 - 181
- [9] An integrated environment for technology closure of deep-submicron IC designs IEEE DESIGN & TEST OF COMPUTERS, 2004, 21 (01): : 14 - 22
- [10] VERILOG HDL SIMULATOR TARGETS DEEP-SUBMICRON ASIC DESIGNS COMPUTER DESIGN, 1994, 33 (07): : A35 - A35