64-CHANNEL BYTE INTERLEAVER FOR GIGABIT SDH TRANSMISSION-SYSTEMS

被引:4
|
作者
MATSUOKA, S [1 ]
YAMABAYASHI, Y [1 ]
HOHKAWA, K [1 ]
HIRATA, M [1 ]
机构
[1] NIPPON TELEGRAPH & TEL PUBL CORP, ELECTR TECHNOL CORP, ATSUGI, KANAGAWA 24301, JAPAN
关键词
CIRCUIT THEORY AND DESIGN; DIGITAL COMMUNICATION SYSTEMS;
D O I
10.1049/el:19920268
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new circuit configuration of a large-scale byte interleaver that forms a multigigabit STM-N signal directly from STM-1 signals (155.52Mbit/s) is proposed. The circuit based on the conventional bit interleaver, is uniquely equipped with N/8 row-column exchangers. 64-channel byte multiplexing from 125Mbit/s to 8Gbit/s is demonstrated for the first time. The proposed method paves the way for the future large-scale STM-N byte interleaver needed in the synchronous digital hierarchy (SDH).
引用
收藏
页码:427 / 428
页数:2
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