THE LOW-FREQUENCY NOISE BEHAVIOR AT ROOM-TEMPERATURE AND AT 77-K OF PMOSTS FABRICATED ON HIGH-RESISTIVITY SILICON SUBSTRATES

This paper discusses in detail the low-frequency noise behaviour of pMOS transistors fabricated on high-resistivity silicon. The experimentally observed behaviour deviates from the typical behaviour of standard silicon transistors, therefore dedicated models have to be developed. The impact of several parameters such as the device area, the substrate bias, the conduction mode, and the operating temperature is studied. Deep level bulk trapping centres may introduce an additional generation-recombination noise component. It will be demonstrated that by selecting the operating conditions, high-resistivity silicon devices are appropriate for analog circuit applications.